The process of manufacturing electric circuits involves connecting isolated devices through specific electrical paths. When manufacturing silicon integrated circuits (ICs) or chips, therefore, the devices built into the silicon must be isolated from one another. The devices can subsequently be interconnected to create the specific circuit configurations desired. Thus, isolation technology is one of the critical aspects of manufacturing ICs.
A variety of techniques have been developed to isolate devices in ICs. One reason is that different IC types have different isolation requirements. Such types include, for example, NMOS, CMOS, and bipolar. An NMOS or negative-channel metal-oxide semiconductor is a type of semiconductor that is negatively charged so that transistors are turned on or off by the movement of electrons. In contrast, a PMOS (positive-channel MOS) works by moving electron vacancies. An NMOS is faster than a PMOS, but also more expensive to produce.
A CMOS or complementary metal oxide semiconductor uses both NMOS (negative polarity) and PMOS (positive polarity) circuits. Because only one of the circuit types is on at any given time, CMOS chips require less power than chips using just one type of transistor. This makes CMOS chips particularly attractive for use in battery-powered devices, such as portable computers. Personal computers also contain a small amount of battery-powered CMOS memory to hold the date, time, and system setup parameters.
The bipolar transistor is an electronic device with two pn junctions in close proximity. There are three device regions: an emitter, a base (the middle region), and a collector. The two pn junctions (i.e., the emitter-base and collector-base junctions) are in a single bar of semiconductor material, separated by a distance. Modulation of the current flow in one pn junction by changing the bias of the nearby junction is called bipolar-transistor action. External leads can be attached to each of the three regions, and external voltages and currents can be applied to the device from these leads.
These and other different IC types require different isolation technologies. In addition, the various isolation technologies have different attributes with respect to minimum isolation spacing, surface planarity, process complexity, and density of defects generated during manufacture of the isolation structure. Tradeoffs must be made among these characteristics when selecting an appropriate isolation technology for a particular circuit application.
Historically, because bipolar ICs were the first to be developed, a technology for isolating the collector regions of the bipolar devices was also the first to be invented (called junction isolation, a term including structures that are isolated by an oxide along the side walls and by a junction at the bottom). PMOS and NMOS ICs did not need junction isolation; nevertheless, it was still necessary to provide an isolation structure that would prevent the establishment of parasitic channels between adjacent devices. The most important technique developed was called LOCOS isolation (for LOCal Oxidation of Silicon), which involved the formation of a semi-recessed oxide in the nonactive areas of the substrate.
As device geometries reached submicron size, conventional LOCOS isolation technologies reached the limits of their effectiveness. Therefore, alternative isolation processes for CMOS and bipolar technologies were needed. Modified LOCOS processes, which overcome some of the drawbacks of conventional LOCOS for small-geometry devices; trench isolation; and selective-epitaxial isolation—all were among the newer approaches adopted.
Devices that must function under high voltages and in harsh radiation environments require even more stringent isolation technologies. Junction isolation is not suitable for high-voltage applications because at supply voltages of +30 volts junction breakdown occurs under reasonable doping levels and device-structure dimensions. Transient photocurrents produced in pn junctions by gamma rays render junction isolation ineffective in high-radiation environments. For such applications, a preferred isolation technique is one that depends on completely surrounding devices with an insulator, rather than with a pn junction.
These techniques are generally termed silicon-on-insulator (“SOI”) isolation processes. Included within SOI isolation processes are older approaches such as dielectric isolation (“DI”) and silicon-on-sapphire (“SOS”). Also included are more recently developed technologies: separation by implanted oxygen (“SIMOX”), zone-melting-recrystallization (“ZMR”), full isolation by porous-oxidized silicon (“FIPOS”), and wafer bonding. The SOI process was developed by International Business Machines Corporation.
Unlike CMOS-based chips that are doped with impurities enabling the chip to store capacitance that must be discharged and recharged, SOI chips are formed by setting transistors on a thin silicon layer that is separated from the silicon substrate by an insulator layer of thin silicon oxide or glass, which minimizes capacitance (or the energy absorbed from the transistor). Full isolation is provided.
SOI isolation offers many advantages. In some cases, the SOI technique uses simpler manufacturing sequences and yields an improved cross-section compared to circuits fabricated on bulk silicon. These advantages are illustrated in FIGS. 1A and 1B, which compare a mesa-isolated SOI CMOS process (FIG. 1B) with a p-well bulk CMOS process (FIG. 1A). SOI isolation also provides reduced capacitive coupling between various circuit elements over the entire IC and, in CMOS circuits, latch up is eliminated. SOI isolation may reduce chip size, increase packing density, or both. Minimum device separation is determined only by the limitation of lithography. Finally, reductions in parasitic capacitance and chip size allow the SOI process to provide increased circuit speed.
When an SOI technology based on a thin silicon film is used, two other important advantages can be obtained. First, a relatively benign surface topography (for step coverage) is produced if device isolation can be achieved by a complete island, sloped-etch wall process of the thin silicon film. Second, because SOI isolation techniques eliminate the parasitic field of the field effect transistor (“FET”) between adjacent devices, LOCOS processes are not needed.
As with all isolation technologies, SOI isolation has its disadvantages. For example, active-device regions in SOI technologies tend to be poorer in crystalline quality than their counterparts in bulk silicon. More relevant to the present invention, the presence of an insulator layer tends to complicate or prevent the adoption of effective defect-gettering and impurity-gettering processes. Nevertheless, the advantages of SOI isolation are sufficiently attractive that improvements to the technique have important commercial implications.
To overcome the shortcomings of conventional SOI isolation processes and the devices resulting from such processes, a new process of manufacturing a SOI wafer and the wafer itself are provided. An object of the present invention is to increase the reliability, ease, and efficiency of the process of manufacturing SOI wafers. A related object is to widen the lithographic focus window of the manufacturing process. Another object is to reduce the time required to market SOI wafers. It is still another object of the present invention to positively impact photoresist thickness and stepper manufacturer selection during manufacture.
An additional object of the present invention is to incorporate improved SOI wafers into such applications as optical switches. A related object is to increase the speed of optical switches. Yet another object of this invention is to reduce power consumption.